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lt3791-1 1 37911f typical a pplica t ion fea t ures descrip t ion 60v 4-switch synchronous buck-boost controller the lt ? 3791-1 is a synchronous 4- switch buck - boost volt - age/ current regulator controller. the controller can regulate output voltage, output current, or input current with input voltages above, below, or equal to the output voltage. the constant-frequency, current mode architecture allows its frequency to be adjusted or synchronized from 200 khz to 700khz. no top fet refresh switching cycle is needed in buck or boost operation. with 60 v input, 60 v output capability and seamless transitions between operating regions, the lt3791-1 is ideal for voltage regulator, bat- tery/super-capacitor charger applications in automotive, industrial, telecom, and even battery-powered systems. the lt3791-1 provides input current monitor, output current monitor, and various status flags, such as c/10 charge termination and shorted output flag. l, lt , lt c , lt m , linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. 120w (24v 5a) buck-boost voltage regulator a pplica t ions n 4-switch single inductor architecture allows v in above, below or equal to v out n synchronous switching: up to 98.5% efficiency n wide v in range: 4.7v to 60v n 2% output voltage accuracy: 1.2v v out < 60v n 6% output current accuracy: 0v v out < 60v n input and output current regulation with current monitor outputs n no top fet refresh in buck or boost n v out disconnected from v in during shutdown n c/10 charge termination and output shorted flags n capable of 100w or greater per ic n 38-lead tssop with exposed pad efficiency vs load current n automotive, t elecom, industrial systems n high power battery-powered system load current (a) 0 1 efficiency (%) 90 95 100 37911 ta01b 80 70 60 85 75 65 2 3 4 5 v in = 12v v in = 24v v in = 54v v in 12v to 58v intv cc tg1 bg1 snsp snsn bst1 bst2 bg2 pgnd sw2 tg2 rt lt3791-1 swi short c/10 ccm 470nf ivinn v in ivinp ivinmon ismon clkout pwmout test1 en/uvlo ovlo v ref pwm ctrl 147k 200khz v c syncss sgnd 1f 499k 56.2k 100k 499k 27.4k intv cc 0.1f 33nf 10nf 37911 ta01a 0.004 isp isn fb 0.1f 10h 0.1f 4.7f 4.7f 50v 2 4.7f 100v 47f 80v 0.015 v out 24v 5a 73.2k 3.83k 5.1k + 220f 35v + 100k 200k 0.003 50
lt3791-1 2 37911f p in c on f igura t ion a bsolu t e maxi m u m r a t ings supply voltages input supply (v in ) ..................................................... 60 v sw 1, sw2 ...................................................... C1 v to 60 v c /10 , short ............................................................. 15 v en / u vlo , ivinp , ivinn , isp , isn .............................. 60 v in tv cc , ( bst 1- sw 1), ( bst 2- sw 2) ............................. 6 v ccm , sync , rt, ctrl , ovlo , pwm .......................... 6 v ivinmon , ismon , fb , ss , vc , v ref ........................... 6v iv inp - ivinn , isp - isn , snsp - snsn ....................... 0.5 v snsp , snsn ........................................................... 0.3 v operating junction temperature ( notes 2, 3) lt 3791 e -1/ lt 3791 i -1 ......................... C 40 c to 125 c lt 3791 h -1 ......................................... C 40 c to 150 c lt 379 1 mp -1 ....................................... C55 c to 150 c storage temperature range .................. C 65 c to 150 c lead temperature ( soldering , 10 sec ) ................... 30 0 c (note 1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 top view fe package 38-lead plastic tssop 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 ctrl ss pwm c/10 short v ref ismon ivinmon en/uvlo ivinp ivinn v in intv cc tg1 bst1 sw1 pgnd bg1 bg2 ovlo fb v c rt sync clkout ccm pwmout sgnd test1 snsn snsp isn isp tg2 nc bst2 sw2 pgnd 39 sgnd t jmax = 150c, ja = 28c/w exposed pad (pin 39) is sgnd, must be soldered to pcb e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v in = 12v, v en/uvlo = 12v unless otherwise noted. o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range lt3791efe-1#pbf lt3791efe-1#trpbf lt3791fe-1 38-lead plastic tssop C40c to 125c lt3791ife-1#pbf lt3791ife-1#trpbf lt3791fe-1 38-lead plastic tssop C40c to 125c lt3791hfe-1#pbf lt3791hfe-1#trpbf lt3791fe-1 38-lead plastic tssop C40c to 150c lt3791mpfe-1#pbf lt3791mpfe-1#trpbf lt3791fe-1 38-lead plastic tssop C55c to 150c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ parameter conditions min typ max units input v in operating voltage 4.7 60 v v in shutdown i q v en/uvlo = 0v 0.1 1 a v in operating i q (not switching) fb = 1.3v, r t = 59.0k 3.0 4 ma
lt3791-1 3 37911f e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v in = 12v, v en/uvlo = 12v unless otherwise noted. parameter conditions min typ max units logic inputs en/uvlo falling threshold l 1.16 1.2 1.24 v en/uvlo rising hysteresis 15 mv en/uvlo input low voltage i vin drops below 1 a 0.3 v en/uvlo pin bias current low v en/uvlo = 1v 2 3 4 a en/uvlo pin bias current high v en/uvlo = 1.6v 10 100 na ccm threshold voltage 0.3 1.5 v ctrl input bias current v ctrl = 1v 20 50 na ctrl latch-off threshold 175 mv ovlo rising shutdown voltage l 2.85 3 3.15 v ovlo falling hysteresis 75 mv regulation v ref voltage l 1.96 2.00 2.04 v v ref line regulation 4.7v < v in < 60v 0.002 0.04 %/v v (isp-isn) threshold v ctrl = 2v l 97.5 94 100 100 102.5 106 mv mv v ctrl = 1100mv l 87 84 90 90 93 96 mv mv v ctrl = 700mv l 47.5 46 50 50 52.5 54 mv mv v ctrl = 300mv l 6.5 5 10 10 13.5 15 mv mv isp bias current 110 a isn bias current 20 a output current sense common mode range 0 60 v output current sense amplifier g m 890 s ismon monitor voltage v (isp-isn) = 100mv l 0.96 1 1.04 v input current sense threshold v (ivinp-ivinn) 3v v ivinp 60v l 46.5 50 54 mv ivinp bias current 90 a ivinn bias current 20 a input current sense common mode range 3 60 v input current sense amplifier g m 2.12 ms ivinmon monitor voltage v (ivinp-ivinn) = 50mv l 0.96 1 1.04 v fb regulation voltage l 1.194 1.176 1.2 1.2 1.206 1.220 v v fb line regulation 4.7v < v in < 60v 0.002 0.025 %/v fb amplifier g m 565 s fb pin input bias current fb in regulation 100 150 na v c standby input bias current pwm = 0v C20 20 na v sense(max) (v snsp-snsn ) boost buck l l 42 C56 51 C47.5 60 C39 mv mv fault ss pull-up current v ss = 0v 14 a ss discharge current 1.4 a
lt3791-1 4 37911f e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v in = 12v, v en/uvlo = 12v unless otherwise noted. parameter conditions min typ max units c/10 rising threshold (v fb ) v (isp-isn) = 0v l 1.127 1.15 1.173 v c/10 falling threshold (v fb ) l 1.078 1.1 1.122 v c/10 falling threshold (v (isp-isn) ) v fb = 1.2v 5 10 15 mv short falling threshold (v fb ) 380 400 450 mv c/10 pin output impedance 1.1 2.0 k short pin output impedance 1.1 2.0 k ss latch-off threshold 1.75 v ss reset threshold 0.2 v oscillator switching frequency r t = 147k r t = 59.0k r t = 29.1k 190 380 665 200 400 700 210 420 735 khz khz khz sync frequency 200 700 khz sync pin resistance to gnd 90 k sync threshold voltage 0.3 1.5 v internal v cc regulator intv cc regulation voltage 4.8 5 5.2 v dropout (v in C intv cc ) i intvcc = C10ma, v in = 5v 240 350 mv intv cc undervoltage lockout 3.1 3.5 3.9 v intv cc current limit v intvcc = 4v 67 ma pwm pwm threshold voltage 0.3 1.5 v pwm pin resistance to gnd 90 k pwmout pull-up resistance 10 20 pwmout pull-down resistance 5 10 nmos drivers tg1, tg2 gate driver on-resistance gate pull-up gate pull-down v bst C v sw = 5v 2.6 1.7 bg1, bg2 gate driver on-resistance gate pull-up gate pull-down v intvcc = 5v 3 1.2 tg off to bg on delay c l = 3300pf 60 ns bg off to tg on delay c l = 3300pf 60 ns tg1, tg2, t off(min) r t = 59.0k 220 260 ns note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the lt 3791e-1 is guaranteed to meet performance from 0c to 125c junction temperature. specification over the -40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the lt 3791i-1 is guaranteed to meet performance specifications over the C40c to 125c operating junction temperature range. the lt 3791h-1 is guaranteed to meet performance specifications over the C40c to 150c operating junction temperature range. the lt 3791mp-1 is guaranteed to meet performance specifications over the C55c to 150c operating junction temperature range. high junction temperatures degrade operating lifetimes. operating lifetime is derated for junction temperatures greater than 125c. note 3: the lt 3791-1 includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed the maximum operating junction temperature when overtemperature protection is active. continuous operation above the specified absolute maximum operating junction temperature may impair device reliability.
lt3791-1 5 37911f typical p er f or m ance c harac t eris t ics intv cc load regulation v ref voltage vs temperature v ref load regulation intv cc dropout voltage vs current, temperature intv cc voltage vs temperature t a = 25c, unless otherwise noted. intv cc current limit vs temperature ldo current (ma) 0 v in -v intvcc (v) 1.0 1.5 40 37911 g01 0.5 0 10 20 30 2.5 2.0 t a = 150c t a = 25c t a = ?50c temperature (c) ?50 intv cc (v) 5.00 5.10 150 37911 g02 4.90 4.80 0 50 100 ?25 25 75 125 5.20 4.95 5.05 4.85 5.15 v in = 60v v in = 12v temperature (c) ?50 0 intv cc current limit (ma) 10 30 40 50 70 0 50 75 37911 g03 20 80 90 60 ?25 25 100 125 150 i load (ma) 0 intv cc (v) 5.75 30 37911 g04 5.00 4.50 10 20 40 4.25 4.00 6.00 5.50 5.25 4.75 50 60 70 temperature (c) ?50 v ref (v) 2.00 2.02 150 37911 g05 1.98 1.96 0 50 100 ?25 25 75 125 2.04 1.99 2.01 1.97 2.03 v in = 60v v in = 12v v in = 4.7v i ref (a) 0 v ref (v) 2.00 2.10 400 37911 g06 1.90 1.80 100 200 300 50 150 250 350 2.20 1.95 2.05 1.85 2.15 v (isp-isn) threshold vs v ctrl v (isp-isn) threshold vs v isp v (isp-isn) threshold vs temperature v ctrl (v) 0 v (isp-isn) (mv) 30 90 100 110 0.4 0.6 1.0 1.2 1.4 37911 g07 10 70 50 20 80 0 60 40 0.2 0.8 1.81.6 2.0 v isp (v) 0 v (isp-isn) (mv) 98 100 102 30 50 37911 g08 96 94 92 10 20 40 104 106 108 60 temperature (c) ?50 v (isp-isn) (mv) 100 104 150 37911 g09 96 92 0 50 100 ?25 25 75 125 108 v in = 12v 98 102 94 106 v isp = 60v v isp = 12v v isp = 0v
lt3791-1 6 37911f v (isp-isn) threshold vs v fb ismon voltage vs temperature ismon voltage vs v (isp-isn) v (ivinp-ivinn) threshold vs temperature v (ivinp-ivinn) threshold vs v fb v (ivinp-ivinn) threshold vs v ivinp ivinmon voltage vs temperature fb regulation voltage vs temperature short threshold vs temperature v fb (v) 1.17 0 v (isp-isn) (mv) 20 40 60 80 120 1.18 1.19 1.20 1.21 37911 g10 1.22 1.23 100 temperature (c) ?50 v ismon (v) 1.00 1.02 150 37911 g11 0.98 0.96 0 50 100 ?25 25 75 125 1.04 0.99 1.01 0.97 1.03 v in = 12v v (isp-isn) = 100mv v (isp-isn) (mv) 0 v ismon (v) 0.6 0.8 1.0 80 37911 g12 0.4 0.2 0.5 0.7 0.9 0.3 0.1 0 2010 4030 60 70 90 50 100 temperature (c) ?50 v (ivinp - ivinn) (mv) 50 52 54 25 50 75 100 125 37911 g13 48 46 ?25 0 150 44 42 56 v ivinp = 60v v ivinp = 3v v ivinp (v) 0 v (ivinp - ivinn) (mv) 49.5 50.0 50.5 30 50 37911 g14 49.0 48.5 48.0 10 20 40 51.0 51.5 52.0 60 temperature (c) ?50 v ivinmon (v) 1.00 1.02 150 37911 g15 0.98 0.96 0 50 100 ?25 25 75 125 1.04 0.99 1.01 0.97 1.03 v ivinp = 12v v (ivinp-vinn) = 50mv v fb (v) 1.17 0 v (ivinp-ivinsn) (mv) 10 20 30 40 60 1.18 1.19 1.20 1.21 37911 g16 1.22 1.23 50 temperature (c) ?50 v fb (v) 1.20 1.22 150 37911 g17 1.18 1.16 0 50 100 ?25 25 75 125 1.24 1.19 1.21 1.17 1.23 v in = 60v v in = 12v v in = 4.7v temperature (c) ?50 fb voltage (v) 0.400 0.450 150 37911 g18 0.350 0.300 0 50 100 ?25 25 75 125 0.500 0.375 0.425 0.325 0.475 rising falling typical p er f or m ance c harac t eris t ics t a = 25c, unless otherwise noted.
lt3791-1 7 37911f c/10 threshold vs temperature ovlo threshold vs temperature soft-start current vs temperature supply current vs input voltage en/uvlo pin current en/uvlo threshold voltage temperature (c) ?50 fb voltage (v) 1.100 1.150 150 37911 g19 1.050 1.000 0 50 100 ?25 25 75 125 1.200 1.075 1.125 1.025 1.175 rising falling temperature (c) ?50 ovlo threshold (v) 2.9 3.1 150 37911 g20 2.7 2.5 0 50 100 ?25 25 75 125 3.3 2.8 3.0 2.6 3.2 rising falling temperature (c) ?50 i ss (a) 8 12 150 37911 g21 4 0 0 50 100 ?25 25 75 125 16 6 10 2 14 charging discharging v in (v) 0 i q (ma) 1.5 2.0 2.5 30 50 37911 g22 1.0 0.5 0 10 20 40 3.0 3.5 4.0 60 t a = 150c t a = 25c t a = ?50c temperature (c) ?50 en/uvlo pin current (a) 4 6 150 37911 g23 2 0 0 50 100 ?25 25 75 125 8 3 5 1 7 v en/ulo = 1v temperature (c) ?50 1.10 en/uvlo threshold (v) 1.12 1.16 1.18 1.20 1.30 1.24 0 50 75 37911 g24 1.14 1.26 1.28 1.22 ?25 25 100 125 150 rising falling oscillator frequency vs temperature tg1, tg2 minimum on-time vs temperature tg1, tg2 minimum off-time vs temperature temperature (c) ?50 switching frequency (khz) 400 600 150 37911 g25 200 0 0 50 100 ?25 25 75 125 800 300 500 100 700 r t = 29.1k r t = 59.0k r t = 147k temperature (c) ?50 tg1, tg2 minimum on-time (ns) 60 80 150 37911 g26 40 20 0 50 100 ?25 25 75 125 100 50 70 30 90 tg1 tg2 temperature (c) ?50 tg1, tg2 minimum off-time (ns) 200 250 300 100 125 37911 g27 150 100 ?25 0 25 50 75 150 50 0 350 f sw = 200khz f sw = 400khz f sw = 700khz typical p er f or m ance c harac t eris t ics t a = 25c, unless otherwise noted.
lt3791-1 8 37911f v (bst1-sw1) , v (bst2-sw2) uvlo vs temperature bg1, bg2 driver on-resistance vs temperature tg1, tg2 driver on-resistance vs temperature pwmout on-resistance vs temperature v c voltage vs duty cycle v (snsp-snsn) buck threshold vs v c v (snsp-snsn) buck threshold vs temperature v (snsp-snsn) boost threshold vs v c v (snsp-snsn) boost threshold vs temperature temperature (c) ?50 v (bst1-sw1) , v (bst2,sw2) (v) 3.5 3.7 150 37911 g28 3.3 3.1 0 50 100 ?25 25 75 125 3.9 3.4 3.6 3.2 3.8 rising falling temperature (c) ?50 bg1, bg2 resistance () 2.5 3.0 3.5 150 37911 g29 2.0 1.5 0 0 50 100 ?25 25 75 125 0.5 1.0 4.5 4.0 pull-up pull-down temperature (c) ?50 tg1, tg2 resistance () 2.0 3.0 150 37911 g30 1.0 0 0 50 100 ?25 25 75 125 4.0 1.5 2.5 0.5 3.5 pull-up pull-down temperature (c) ?50 pwmout resistance () 8 10 12 100 125 37911 g31 6 4 ?25 0 25 50 75 150 2 0 14 pull-up pull-down duty cycle (%) 0 v c (v) 0.6 0.8 1.0 60 100 37911 g32 0.4 0.2 0 20 40 80 1.2 1.4 1.6 bg2 bg1 v (snsp-snsn) = 0v v c (v) 0.6 ?60 v (snsp-snsn) (mv) ?40 ?20 0 20 60 0.8 1.0 1.2 1.4 37911 g33 1.6 1.8 40 temperature (c) ?50 ?60 v (snsp-snsn) threshold (mv) ?40 ?20 0 20 0 50 100 150 37911 g34 40 60 ?25 25 75 125 v c(min) v c(max) v c (v) 0.6 60 40 20 0 ?20 ?40 ?60 ?80 1.2 1.6 37911 g35 0.8 1.0 1.4 1.8 v (snsp-snsn) (mv) temperature (c) ?50 v (snsp-snsn) threshold (mv) 0 20 40 100 125 37911 g36 ?20 ?40 ?25 0 25 50 75 150 ?60 ?80 60 v c(max) v c(min) typical p er f or m ance c harac t eris t ics t a = 25c, unless otherwise noted.
lt3791-1 9 37911f p in func t ions ctrl ( pin 1): output current sense threshold adjustment pin. regulating threshold v (isp-isn) is 1/10 th of (v ctrl C 200mv). ctrl linear range is from 200 mv to 1.1 v. for v ctrl > 1.3 v, the current sense threshold is constant at the full-scale value of 100 mv. for 1.1v < v ctrl < 1.3 v, the dependence of the current sense threshold upon v ctrl tran- sitions from a linear function to a constant value, reaching 98% of full scale by v ctrl = 1.2 v. connect ctrl to v ref for the 100 mv default threshold. force less than 175mv (typical) to stop switching. do not leave this pin open. ss (pin 2): soft-start reduces the input power sources surge current by gradually increasing the controllers cur- rent limit. a minimum value of 22 nf is recommended on this pin. a 100 k resistor must be placed between ss and v ref for the lt3791-1. pwm (pin 3): a signal low turns off switches, idles switch- ing and disconnects the v c pin from all external loads. the pwmout pin follows the pwm pin. pwm has an internal 90k pull-down resistor. if not used, connect to intv cc . c/10 (pin 4): c/10 charge termination pin. an open-drain pull -down on c/10 asserts if fb is greater than 1.15v (typi- cal) and v (isp-isn) is less than 10mv (typical). to function, the pin requires an external pull-up resistor. short (pin 5): output shorted pin. an open-drain pull- down on short asserts if fb is less than 400 mv ( typical ) . to function, the pin requires an external pull-up resistor. v ref (pin 6): voltage reference output pin, typically 2 v. this pin drives a resistor divider for the ctrl pin, either for output current adjustment or for temperature limit/ compensation of the output load. can supply up to 200a of current. ismon (pin 7): monitor pin that produces a voltage that is ten times the voltage v (isp-isn) . ismon will equal 1v when v (isp-isn) = 100mv. ivinmon (pin 8): monitor pin that produces a voltage that is twenty times the voltage v (ivinp-ivinn) . ivinmon will equal 1v when v (ivinp-ivinn) = 50mv. en/uvlo (pin 9): enable control pin. forcing an accurate 1.2v falling threshold with an externally programmable hysteresis is generated by the external resistor divider and a 3 a pull-down current. above the 1.2v (typical) threshold ( but below 6 v), en/ uvlo input bias current is sub-a. below the falling threshold, a 3 a pull-down cur- rent is enabled so the user can define the hysteresis with the external resistor selection. an undervoltage condition resets soft-start. tie to 0.3 v, or less, to disable the device and reduce v in quiescent current below 1 a. ivinp (pin 10): positive input for the input current limit and monitor. input bias current for this pin is typically 90 a. ivinn (pin 11): negative input for the input current limit and monitor. the input bias current for this pin is typically 20a. v in (pin 12): main input supply. bypass this pin to pgnd with a capacitor. intv cc (pin 13): internal 5 v regulator output. the driver and control circuits are powered from this voltage. bypass this pin to pgnd with a minimum 4.7 f ceramic capacitor. tg 1 (pin 14): top gate drive. drives the top n-channel mosfet with a voltage equal to intv cc superimposed on the switch node voltage sw1. bst1 (pin 15): bootstrapped driver supply. the bst1 pin swings from a diode voltage below intv cc up to a diode voltage below v in + intv cc . sw1 (pin 16): switch node. sw1 pin swings from a diode voltage drop below ground up to v in . pgnd (pins 17, 20): power ground. connect these pins closely to the source of the bottom n-channel mosfet. bg1 (pin 18): bottom gate drive. drives the gate of the bottom n-channel mosfet between ground and intv cc . bg2 (pin 19): bottom gate drive. drives the gate of the bottom n-channel mosfet between ground and intv cc . sw2 (pin 21): switch node. sw2 pin swings from a diode voltage drop below ground up to v out .
lt3791-1 10 37911f p in func t ions bst2 (pin 22): bootstrapped driver supply. the bst2 pin swings from a diode voltage below intv cc up to a diode voltage below v out + intv cc . nc (pin 23): no connect pin. leave this pin floating. tg 2 (pin 24): top gate drive. drives the top n-channel mosfet with a voltage equal to intv cc superimposed on the switch node voltage sw2. isp (pin 25): connection point for the positive terminal of the output current feedback resistor. isn (pin 26): connection point for the negative terminal of the output current feedback resistor. snsp (pin 27): the positive input to the current sense comparator. the v c pin voltage and controlled offsets between the snsp and snsn pins, in conjunction with a resistor, set the current trip threshold. snsn (pin 28): the negative input to the current sense comparator. test1 (pin 29): this pin is used for testing purposes only and must be connected to sgnd for the part to operate properly. sgnd (pin 30, exposed pad pin 39): signal ground. all small-signal components and compensation should connect to this ground, which should be connected to pgnd at a single point. solder the exposed pad directly to the ground plane. pwmout (pin 31): buffered version of pw m signal for driving output load disconnect n-channel mosfet. the pwmout pin is driven from intv cc . use of a mosfet with a gate cutoff voltage higher than 1 v is recommended. ccm (pin 32): continuous conduction mode pin. when the pin voltage is higher than 1.5 v, the part runs in fixed frequency forced continuous conduction mode and al- lows the inductor current to flow negative. when the pin voltage is less than 0.3 v, the part runs in discontinuous conduction mode and does not allow the inductor current to flow backward. this pin is only meant to block inductor reverse current, and should only be pulled low when the output current is low. this pin must be either connected to intv cc (pin 13) for continuous conduction mode across all loads, or it must be connected to the c/10 (pin 4) with a pull-up resistor to intv cc for continuous conduction mode at heavy load and for discontinuous conduction mode at light load. clkout (pin 33): clock output pin. a 180 out-of-phase clock is provided at the oscillator frequency to allow for par - alleling two devices for extending output power capability. sync (pin 34): external synchronization input pin. this pin is internally terminated to gnd with a 90 k resistor. the internal buck clock is synchronized to the rising edge of the sync signal while the internal boost clock is 180 phase shifted. rt (pin 35): frequency set pin. place a resistor to gnd to set the internal frequency. the range of oscillation is 200khz to 700khz. v c (pin 36): current control threshold and error amplifier compensation point. the current comparator threshold increases with this control voltage. the voltage ranges from 0.7v to 1.9v. fb (pin 37): voltage loop feedback pin. fb is intended for constant- voltage regulation. the internal transconductance amplifier with output v c will regulate fb to 1.2v (typical) through the dc/dc converter. if the fb input is regulat- ing the loop and v (isp-isn) < 10 mv, the c/10 pull-down is asserted. if the fb pin is less than 400 mv, the short pull-down is asserted. ovlo (pin 38): overvoltage input pin. this pin is used for ovlo, if ovlo > 3 v then ss is pulled low, the part stops switching and resets. do not leave this pin open.
lt3791-1 11 37911f b lock diagra m 0.2v 1.15v 0.4v fb ? + a18 ? + a9 3v ? + ? + ? + ? + a8 a6 a5 1.75v 1.4a v c ovlo 37911 bd 38 36 ss 2 pwmout pwm a17 intv cc 31 sgnd 30, 39 c/10 4 3 ? + + + ? ? a12 1.2v 14a 3a shdn_int v ref a11 a10 a16 a15 ismon_int ivinmon_int ctrl 1 fb 37 snsn 28 snsp 27 bst2 22 tg2 sw2 intv cc intv cc 21 short 5 q ss reset ss latch r s 24 a13 sw1 16 tg1 bst1 15 14 bg2 19 a14 bg1 pwm 18 pgnd 17 buck logic ? + a7 ? + a3 ? + a4 ss latch ss_reset shdn_int osc slope_comp_boost slope_comp_buck 1.2v en/uvlo 9 ivinmon 8 ismon ismon_int 7 isp 25 isn 26 rt 35 ccm 32 sync 34 clkout 33 ? + a2 ivinmon_int ivinp ivinn 10 11 v in shdn_int 12 v ref 6 intv cc 13 ? + a1 boost logic regs a = 10 a = 10 a = 20 a = 24 tsd
lt3791-1 12 37911f o pera t ion the lt3791-1 is a current mode controller that provides an output voltage above, equal to or below the input voltage. the lt c proprietary topology and control architecture uses a current sensing resistor in buck or boost operation. the sensed inductor current is controlled by the voltage on the v c pin, which is the output of the feedback amplifiers a11 and a12. the v c pin is controlled by three inputs, one input from the output current loop, one input from the input current loop, and the third input from the feedback loop. whichever feedback input is higher takes precedence , forcing the converter into either a constant-current or a constant-voltage mode. the lt3791-1 is designed to transition cleanly between the two modes of operation. current sense amplifier a1 senses the voltage between the ivinp and ivinn pins and provides a pre-gain to amplifier a11. when the voltage between ivinp and ivinn reaches 50 mv, the output of a1 provides ivinmon_int to the inverting input of a11 and the converter is in constant-current mode. if the current sense voltage exceeds 50 mv, the output of a1 increases causing the output of a11 to decrease, thus reducing the amount of current delivered to the output. in this manner the current sense voltage is regulated to 50mv. the output current amplifier works similar to the input current amplifier but with a 100 mv voltage instead of 50mv. the output current sense level is also adjustable by the ctrl pin. forcing ctrl to less than 1.2 v forces ismon_int to the same level as ctrl, thus providing current- level control. the output current amplifier provides rail-to-rail operation. similarly if the fb pin goes above 1.2v the output of a11 decreases to reduce the current level and regulate the output (constant-voltage mode). the lt3791-1 provides monitoring pins ivinmon and ismon that are proportional to the voltage across the input and output current amplifiers respectively. the main control loop is shut down by pulling the en/ uvlo pin low. when the en/uvlo pin is higher than 1.2 v, an internal 14 a current source charges soft-start capaci- tor c ss at the ss pin. the v c voltage is then clamped a diode voltage higher than the ss voltage while the c ss is slowly charged during start-up. this soft-start clamping prevents abrupt current from being drawn from the input power supply. the top mosfet drivers are biased from floating boot- strap capacitors c 1 and c 2, which are normally recharged through an external diode when the top mosfet is turned off. a unique charge sharing technique eliminates top fet refresh switching cycle in buck or boost operation. schottky diodes across the synchronous switch m 4 and synchronous switch m 2 are not required, but they do provide a lower drop during the dead time. the addition of the schottky diode typically improves peak efficiency by 1% to 2% at 500khz. power switch control figure 1 shows a simplified diagram of how the four power switches are connected to the inductor, v in , v out and gnd. figure 2 shows the regions of operation for the lt3791-1 as a function of duty cycle d. the power switches are properly controlled so the transfer between regions is continuous. when v in approaches v out , the buck-boost region is reached. buck region (v in > v out ) switch m4 is always on and switch m3 is always off during this mode. at the start of every cycle, synchronous switch m2 is turned on first. inductor current is sensed when synchronous switch m2 is turned on. after the sensed inductor current falls below the reference voltage, which is proportional to v c , synchronous switch m2 is turned off and switch m1 is turned on for the remainder of the cycle. switches m1 and m2 will alternate, behaving like a typical m1 sw1 v in v out m2 tg2 bg2 m4 sw2 m3 tg1 bg1 r sense 37911 f01 l1 d max boost (bg2) m1 on, m2 off pwm m3, m4 switches boost region m4 on, m3 off pwm m2, m1 switches buck region 37911 f02 4-switch pwm buck-boost region d min boost d max buck (tg1) d min buck figure 1. simplified diagram of the output switches figure 2. operating regions vs duty cycle
lt3791-1 13 37911f o pera t ion synchronous buck regulator. the duty cycle of switch m1 increases until the maximum duty cycle of the converter in buck operation reaches d max(buck, tg1) , given by: d max(buck,tg1) = 100% C d (buck-boost) where d (buck-boost) is the duty cycle of the buck-boost switch range: d (buck-boost) = 8% figure 3 shows typical buck operation waveforms. if v in approaches v out , the buck-boost region is reached. buck-boost region (v in ~ v out ) when v in is close to v out , the controller is in buck-boost operation. figure 4 and figure 5 show typical waveforms in this operation. every cycle the controller turns on switches m2 and m4, then m1 and m4 are turned on until 180 later when switches m1 and m3 turn on, and then switches m1 and m4 are turned on for the remainder of the cycle. boost region (v in < v out ) switch m 1 is always on and synchronous switch m 2 is al- ways off in boost operation. every cycle switch m 3 is turned on first. inductor current is sensed when synchronous switch m 3 is turned on. after the sensed inductor current exceeds the reference voltage which is proportional to v c , switch m 3 turns off and synchronous switch m 4 is turned on for the remainder of the cycle. switches m 3 and m 4 alternate , behaving like a typical synchronous boost regulator. the duty cycle of switch m3 decreases until the minimum duty cycle of the converter in boost operation reaches d min(boost,bg2) , given by: d min(boost,bg2) = d (buck-boost) where d (buck-boost) is the duty cycle of the buck-boost switch range: d (buck-boost) = 8% figure 6 shows typical boost operation waveforms. if v in approaches v out , the buck-boost region is reached. low current operation the lt3791-1 is recommended to run in forced continuous conduction mode at heavy load by pulling the ccm pin higher than 1.5 v. in this mode the controller behaves as a continuous, pwm current mode synchronous switching regulator. in boost operation, switch m1 is always on, switch? m3 and synchronous switch m4 are alternately turned on to maintain the output voltage independent of the direction of inductor current. in buck operation, synchronous switch m4 is always on, switch m1 and syn- chronous switch m2 are alternately turned on to maintain the output voltage independent of the direction of inductor current. in the forced continuous mode , the output can sour ce or sink current. however, reverse inductor current from the output to the input is not desired for certain applications. for these ap- plications, the ccm pin must be connected to c/10 (pin 4) with a pull-up resistor to intv cc ( see front page typical application). therefore, the ccm pin will be pulled lower than 0.3 v for discontinuous conduction mode by the c/10 pin when the output current is low. in this mode, switch m4 turns off when the inductor current flows negative. figure 3. buck operation (v in > v out ) m2 + m4 m2 + m4 m2 + m4 m1 + m4 37911 f03 m1 + m4 m1 + m4 figure 4. buck-boost operation (v in v out ) figure 5. buck-boost operation (v in v out ) m2 + m4 m2 + m4 m2 + m4 m1 + m4 m1 + m4 m1 + m4 m1 + m4 m1 + m4 m1 + m4 m1+ m3 m1+ m3 m1+ m3 37911 f04 m2 + m4 m2 + m4 m2 + m4 m1 + m4 m1 + m4 m1 + m4 m1 + m4 m1 + m4 m1 + m4 m1 + m3 m1 + m3 m1 + m3 37911 f05 m1 + m3 m1 + m3 m1 + m4 m1 + m4 m1 + m3 m1 + m4 37911 f06 figure 6. boost operation (v in < v out )
lt3791-1 14 37911f a pplica t ions i n f or m a t ion the typical application on the front page is a basic lt3791 -1 application circuit. external component selection is driven by the load requirement, and begins with the selection of r sense and the inductor value. next, the power mosfets are selected. finally, c in and c out are selected. this circuit can operate up to an input voltage of 60v. programming the switching frequency the rt frequency adjust pin allows the user to program the switching frequency from 200 khz to 700 khz to optimize efficiency/ performance or external component size. higher frequency operation yields smaller component size but increases switching losses and gate driving current, and may not allow sufficiently high or low duty cycle operation. lower frequency operation gives better performance at the cost of larger external component size. for an appropriate r t resistor value see table 1. an external resistor from the rt pin to gnd is required; do not leave this pin open. table 1. switching frequency vs r t value f osc (khz) r t (k) 200 147 300 84.5 400 59.0 500 45.3 600 35.7 700 29.4 frequency synchronization the lt3791-1 switching frequency can be synchronized to an external clock using the sync pin. driving sync with a 50% duty cycle waveform is always a good choice, otherwise maintain the duty cycle between 10% and 90%. the falling edge of clkout corresponds to the rising edge of sync thus allowing 2- phase paralleling converters. the rising edge of clkout turns on switch m3 and the falling edge of clkout turns on switch m2. inductor selection the operating frequency and inductor selection are inter- related in that higher operating frequencies allow the use of smaller inductor and capacitor values. the inductor value has a direct effect on ripple current. the maximum inductor current ripple i l can be seen in figure 7. this is the maximum ripple that will prevent subharmonic oscillation and also regulate with zero load. the ripple should be less than this to allow proper operation over all load currents. for a given ripple the inductance terms in continuous mode are as follows: l buck > v out ? v in(max) ? v out ( ) ? 100 f ? i out(max) ? %ripple ? v in(max) l boost > v in(min) 2 ? v out ? v in(min) ( ) ? 100 f ? i out(max) ? %ripple ? v out 2 where: f is operating frequency % ripple is allowable inductor current ripple v in(min) is minimum input voltage v in(max) is maximum input voltage v out is output voltage i out(max) is maximum output load current for high efficiency, choose an inductor with low core loss. also, the inductor should have low dc resistance to reduce the i 2 r losses, and must be able to handle the peak inductor current without saturating. to minimize radiated noise, use a shielded inductor. r sense selection and maximum output current r sense is chosen based on the required output current. the current comparator threshold sets the peak of the inductor bg1, bg2 duty cycle (%) 50 ? i l /i sense(max) (%) 120 160 200 90 37911 f07 80 40 100 140 180 60 20 0 6055 7065 80 85 95 75 100 boost ?i l / i sense(max) limit buck ?i l / i sense(max) limit figure 7. maximum peak-to-peak ripple vs duty cycle
lt3791-1 15 37911f a pplica t ions i n f or m a t ion current in boost operation and the maximum inductor valley current in buck operation. in boost operation, the maximum average load current at v in( min) is: i out(max _ boost) = 51mv r sense ? ? i l 2 ? ? ? ? ? ? ? v in(min) v out where i l is peak-to-peak inductor ripple current. in buck operation, the maximum average load current is: i out(max _ buck) = 47.5mv r sense + ? i l 2 ? ? ? ? ? ? the maximum current sensing r sense value for the boost operation is: r sense(max) = 2 ? 51mv ? v in(min) 2 ? i led ? v out + ? i l(boost) ? v in(min) the maximum current sensing r sense value for the buck operation is: r sense(max) = 2 ? 47.5mv 2 ? i led ? ? i l(buck) the final r sense value should be lower than the calculated r sense(max) in both the boost and buck operation. a 20% to 30% margin is usually recommended. c in and c out selection in boost operation, input current is continuous. in buck operation, input current is discontinuous. in buck opera- tion, the selection of input capacitor, c in , is driven by the need to filter the input square wave current. use a low esr capacitor sized to handle the maximum rms current. for buck operation, the input rms current is given by: i rms = i led 2 ? d + ? i l 2 12 ? d the formula has a maximum at v in = 2 v out . note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to derate the capacitor. in boost operation, the discontinuous current shifts from the input to the output, so c out must be capable of reducing the output voltage ripple. the effects of esr (equivalent series resistance) and the bulk capacitance must be considered when choosing the right capacitor for a given output ripple voltage. the steady ripple due to charging and discharging the bulk capacitance is given by: ? v ripple boost _ cap ( ) = i led ? v out ? v in(min) ( ) c out ? v out ? f ? v ripple buck _ cap ( ) ? i l 8 ? f ? c out where c out is the output filter capacitor. the steady ripple due to the voltage drop across the esr is given by: v boost(esr) = i led ? esr v buck(esr) = i led ? esr multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirements. output capacitors are also used for stability for the lt3791 - 1. a good starting point for output capacitors is seen in the typical applications circuits. ceramic capacitors have excellent low esr characteristics but can have a high voltage coefficient and are recommended for applications less than 100 w. capacitors available with low esr and high ripple current ratings, such as os-con and poscap may be needed for applications greater than 100w. programming v in uvlo and ovlo the falling uvlo value can be accurately set by the resistor divider r1 and r2. a small 3 a pull-down current is active when the en/uvlo is below the threshold. the purpose of this current is to allow the user to program the rising hysteresis. the following equations should be used to determine the resistor values: v in(uvlo ? ) = 1.2 ? r1 + r2 r2 v in(uvlo + ) = 3a ? r1 + 1.215 ? r1 + r2 r2
lt3791-1 16 37911f figure 8. resistor connection to set v in uvlo and ovlo thresholds lt3791-1 v in r1 r3 r4 r2 37911 f08 en/uvlo ovlo the rising ovlo value can be accurately set by the resis- tor divider r3 and r4. the following equations should be used to determine the resistor values: v in(ovlo + ) = 3 ? r3 + r4 r4 v in(ovlo ? ) = 2.925 ? r3 + r4 r4 a pplica t ions i n f or m a t ion table 2. v (isp-isn) threshold vs ctrl v ctrl (v) v (isp-isn) (mv) 1.1 90 1.15 94.5 1.2 98 1.25 99.5 1.3 100 when v ctrl is higher than 1.3 v, the output current is regulated to: i out = 100mv r out the ctrl pin should not be left open ( tie to v ref if not used). the ctrl pin can also be used in conjunction with a thermistor to provide overtemperature protection for the output load, or with a resistor divider to v in to reduce output power and switching current when v in is low. the presence of a time varying differential voltage signal (ripple) across isp and isn at the switching frequency is expected. the amplitude of this signal is increased by high output load current, low switching frequency and/ or a smaller value output filter capacitor. some level of ripple signal is acceptable: the compensation capacitor on the v c pin filters the signal so the average difference between isp and isn is regulated to the user-programmed value. ripple voltage amplitude ( peak-to-peak) in excess of 20 mv should not cause mis-operation, but may lead to noticeable offset between the average value and the user-programmed value. ismon the ismon pin provides a linear indication of the current flowing through the output. the equation for v ismon is v (ispCisn) ? 10. this pin is suitable for driving an adc input, however, the output impedance of this pin is 12.5 k so care must be taken not to load this pin. programming input current limit the lt3791-1 has a standalone current sense amplifier. it can be used to limit the input current. the input current limit is calculated by the following equation: programming output current the output current is programmed by placing an appro- priate value current sense resistor, r out , in series with the output load. the voltage drop across r out is ( kelvin) sensed by the isp and isn pins. the ctrl pin should be tied to a voltage higher than 1.2 v to get the full-scale 100mv ( typical) threshold across the sense resistor. the ctrl pin can also be used to adjust the output current, although relative accuracy decreases with the decreasing sense threshold. when the ctrl pin voltage is less than 1v, the output current is: i out = v ctrl ? 200mv r out ? 10 when the ctrl pin voltage is between 1.1 v and 1.3 v the output current varies with v ctrl , but departs from the equation above by an increasing amount as v ctrl volt- age increases. ultimately, when v ctrl > 1.3 v the output current no longer varies. the typical v (isp-isn) threshold vs v ctrl is listed in table 2.
lt3791-1 17 37911f a pplica t ions i n f or m a t ion i in = 50mv r in for loop stability a lowpass rc filter is needed. for most applications, a 50 resistor and 470 nf capacitor is sufficient. table 3 r in (m) i limit (a) 20 2.5 15 3.3 12 4.2 10 5.0 6 8.3 5 10.0 4 12.5 3 16.7 2 25 ivinmon the ivinmon pin provides a linear indication of the current flowing through the input. the equation for v ivinmon is v (ivinp-ivinn) ? 20. this pin is suitable for driving an adc input, however, the output impedance of this pin is 12.5 k so care must be taken not to load this pin. programming output voltage (constant voltage regulation) for a voltage regulator, the output voltage can be set by selecting the values of r5 and r 6 ( see figure 9) according to the following equation: v out = 1.2 ? r5 + r6 r6 dimming control there are two methods to control the current source for dimming using the lt3791-1. one method uses the ctrl pin to adjust the current regulated in the output. a second method uses the pwm pin to modulate the current source between zero and full current to achieve a precisely pro- grammed average current. to make pwm dimming more accurate, the switch demand current is stored on the v c node during the quiescent phase when pwm is low. this feature minimizes recovery time when the pwm signal goes high. to further improve the recovery time a disconnect switch may be used in the output current path to prevent the isp node from discharging during the pwm signal low phase. the minimum pwm on- or off-time is affected by choice of operating frequency and external component selection. the best overall combination of pwm and analog dimming capabilities is available if the minimum pwm pulse is at least six switching cycles and the pwm pulse is synchronized to the sync signal. short pin the lt3791-1 provides an open- drain status pin , short , which pulls low when the fb pin is below 400mv. the only time the fb pin will be below 400 mv is during start-up or if the output is shorted. during start-up the lt3791-1 ignores the voltage on the fb pin until the soft- start capacitor reaches 1.75v. to prevent false tripping after startup, a large enough soft-start capacitor must be used to allow the output to get up to approximately 40% to 50% of the final value. c/10 pin the lt3791-1 provides an open-drain status pin, c/10, which pulls low when the fb pin is above 1.15 v and the voltage across v (isp-isn) is less than 10 mv. for voltage regulator applications with both isp and isn pins tied together to the output ( i.e., no output current sense and limit), the c/10 pin provides a power good flag. for battery charger applications with output current sense and limit, the c/10 provides a c/10 charge termination flag. figure 9. resistor connection for constant output voltage regulation lt3791-1 v out r5 r6 37911 f09 fb
lt3791-1 18 37911f soft-start soft- start reduces the input power sources surge currents by gradually increasing the controllers current limit (pro- portional to an internally buffered clamped equivalent of v c ). the soft-start interval is set by the soft-start capacitor selection according to the following equation t ss = 1.2v 14a ? c ss a 100 k resistor must be placed between ss and v ref for the lt3791-1. this 100 k resistor also contributes the extra ss charge current. make sure c ss is large enough when there is loading during start-up. loop compensation the lt3791-1 uses an internal transconductance error amplifier whose v c output compensates the control loop. the external inductor, output capacitor and the compensa- tion resistor and capacitor determine the loop stability. the inductor and output capacitor are chosen based on performance, size and cost. the compensation resistor and capacitor at v c are set to optimize control loop response and stability. for typical applications, a 10 nf compensation capacitor at v c is adequate, and a series resistor should always be used to increase the slew rate on the v c pin to maintain tighter regulation of output current during fast transients on the input supply of the converter. power mosfet selections and efficiency considerations the lt3791-1 requires four external n- channel power mosfets, two for the top switches ( switch m 1 and m 4, shown in figure 1) and two for the bottom switches ( switch m 2 and m 3 shown in figure 1). important parameters for the power mosfets are the breakdown voltage, v br( dss) , threshold voltage, v gs( th) , on - resistance, r ds( on) , reverse transfer capacitance, c rss , and maximum current, i ds( max) . the drive voltage is set by the 5 v intv cc supply. con- sequently, logic-level threshold mosfets must be used in lt3791-1 applications. if the input voltage is expected to drop below the 5 v, then sub-logic threshold mosfets should be considered. in order to select the power mosfets, the power dis- sipated by the device must be known. for switch m1, the maximum power dissipation happens in boost operation, when it remains on all the time. its maximum power dis- sipation at maximum output current is given by: p m1(boost) = i led ? v out v in ? ? ? ? ? ? 2 ? t ? r ds(on) where t is a normalization factor ( unity at 25 c) accounting for the significant variation in on-resistance with temperature, typically 0.4%/ c as shown in figure?10. for a maximum junction temperature of 125 c, using a value of t = 1.5 is reasonable. switch m2 operates in buck operation as the synchronous rectifier. its power dissipation at maximum output current is given by: p m2(buck) = v in ? v out v in ? i led 2 ? t ? r ds(on) switch m3 operates in boost operation as the control switch. its power dissipation at maximum current is given by: p m3(boost) = v out ? v in ( ) ? v out v in 2 ? i led 2 ? t ? r ds(on) + k ? v out 3 ? i led v in ? c rss ? f where c rss is usually specified by the mosfet manufac- turers. the constant k, which accounts for the loss caused by reverse-recovery current, is inversely proportional to the gate drive current and has an empirical value of 1.7. for switch m4, the maximum power dissipation happens in boost operation, when its duty cycle is higher than 50%. its maximum power dissipation at maximum output current is given by: p m4(boost) = v in v out ? i led ? v out v in ? ? ? ? ? ? 2 ? t ? r ds(on) for the same output voltage and current, switch m1 has the highest power dissipation and switch m2 has the low- est power dissipation unless a short occurs at the output. a pplica t ions i n f or m a t ion
lt3791-1 19 37911f from a known power dissipated in the power mosfet, its junction temperature can be obtained using the following formula: t j = t a + p ? r th(ja) the r th(ja) to be used in the equation normally includes the r th(jc) for the device plus the thermal resistance from the case to the ambient temperature (r th(jc) ). this value of t j can then be compared to the original, assumed value used in the iterative calculation process. intv cc pin regulator can supply a peak current of 67ma and must be bypassed to ground with a minimum of 4.7 f ceramic capacitor or low esr electrolytic capacitor. an additional 0.1 f ceramic capacitor placed directly adjacent to the intv cc and pgnd ic pins is highly recommended. good bypassing is necessary to supply the high transient current required by mosfet gate drivers. higher input voltage applications in which large mosfets are being driven at high frequencies may cause the maxi- mum junction temperature rating for the lt3791-1 to be exceeded. the system supply current is normally dominated by the gate charge current. additional external loading of the intv cc also needs to be taken into account for the power dissipation calculations. power dissipation for the ic in this case is v in ? i intvcc , and overall efficiency is lowered. the junction temperature can be estimated by using the equations given t j = t a + (p d ? ja ) where ja (in c/w) is the package thermal impedance. for example, a typical application operating in continuous current operation might draw 24ma from a 24v supply: t j = 70c + 24ma ? 24v ? 28c/w = 86c to prevent maximum junction temperature from being exceeded, the input supply current must be checked operating in continuous mode at maximum v in . top gate (tg) mosfet driver supply (c1, d1, c2, d2) the external bootstrap capacitors c1 and c2 connected to the bst1 and bst2 pins supply the gate drive voltage for the topside mosfet switches m1 and m4. when the top mosfet switch m1 turns on, the switch node sw1 rises to v in and the bst1 pin rises to approximately v in + intv cc . when the bottom mosfet switch m 2 turns on, the switch node sw1 drops low and the bootstrap capacitor c1 is charged through d1 from intv cc . when the bottom mosfet switch m3 turns on, the switch node sw2 drops low and the bootstrap capacitor c2, is charged through d2 from intv cc . the bootstrap capacitors c1 and c2 need to store about 100 times the gate charge required by the top mosfet switch m1 and m4. in most applications a 0.1f to 0.47f, x5r or x7r ceramic capacitor is adequate. a pplica t ions i n f or m a t ion figure 10. normalized r ds(on) vs temperature junction temperature (c) ?50 t normalized on-resistance () 1.0 1.5 150 37911 f10 0.5 0 0 50 100 2.0 optional schottky diode (d3, d4) selection the schottky diodes d3 and d4 shown in the typical ap- plications section conduct during the dead time between the conduction of the power mosfet switches. they are intended to prevent the body diode of synchronous switches m2 and m4 from turning on and storing charge during the dead time. in particular, d 4 significantly reduces reverse-recovery current between switch m4 turn-off and switch m3 turn-on, which improves converter efficiency and reduces switch m3 voltage stress. in order for the diode to be effective, the inductance between it and the synchronous switch must be as small as possible, mandat - ing that these components be placed adjacently. intv cc regulator an internal p-channel low dropout regulator produces 5v at the intv cc pin from the v in supply pin. intv cc powers the drivers and internal circuitry within the lt3791-1. the
lt3791-1 20 37911f efficiency considerations the power efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. although all dissipative elements in circuits produce losses, four main sources account for most of the losses in lt3791-1 circuits: 1. dc i 2 r losses. these arise from the resistances of the mosfets, sensing resistor, inductor and pc board traces and cause the efficiency to drop at high output currents. 2. transition loss. this loss arises from the brief amount of time switch m1 or switch m3 spends in the saturated region during switch node transitions. it depends upon the input voltage, load current, driver strength and mosfet capacitance, among other factors. the loss is significant at input voltages above 20 v and can be estimated from: t ransition loss 2.7 ? v in 2 ? i out ? c rss ? f where c rss is the reverse-transfer capacitance. 3. intv cc current. this is the sum of the mosfet driver and control currents. 4. c in and c out loss. the input capacitor has the difficult job of filtering the large rms input current to the regu - lator in buck operation. the output capacitor has the difficult job of filtering the large rms output current in boost operation. both c in and c out are required to have low esr to minimize the ac i 2 r loss and sufficient capacitance to prevent the rms current from causing additional upstream losses in fuses or batteries. 5. other losses. schottky diode d3 and d4 are respon- sible for conduction losses during dead time and light load conduction periods. inductor core loss occurs predominately at light loads. switch m3 causes reverse recovery current loss in boost operation. when making adjustments to improve efficiency, the input current is the best indicator of changes in efficiency. if you make a change and the input current decreases, then the efficiency has increased. if there is no change in the input current, then there is no change in efficiency. pc board layout checklist the basic pc board layout requires a dedicated ground plane layer. also, for high current, a multilayer board provides heat sinking for power components. n the pgnd ground plane layer should not have any traces and it should be as close as possible to the layer with power mosfets. n place c in , switch m1, switch m2 and d1 in one compact area. place c out , switch m3, switch m4 and d2 in one compact area. n use immediate vias to connect the components (in- cluding the lt3791-1s sgnd and pgnd pins) to the ground plane. use several large vias for each power component. n use planes for v in and v out to maintain good voltage filtering and to keep power losses low. n flood a ll unused areas on all layers with copper. flooding with copper will reduce the temperature rise of power components. connect the copper areas to any dc net (v in or pgnd). n separate the signal and power grounds. all small-signal components should return to the sgnd pin at one point, which is then tied to the pgnd pin close to the sources of switch m2 and switch m3. n place switch m2 and switch m3 as close to the control- ler as possible, keeping the pgnd, bg and sw traces short. n keep the high dv/dt sw1, sw2, bst1, bst2, tg1 and tg2 nodes away from sensitive small-signal nodes. a pplica t ions i n f or m a t ion
lt3791-1 21 37911f a pplica t ions i n f or m a t ion n the path formed by switch m1, switch m2, d1 and the c in capacitor should have short leads and pc trace lengths. the path formed by switch m3, switch m4, d2 and the c out capacitor also should have short leads and pc trace lengths. n the output capacitor (C) terminals should be connected as close as possible to the (C) terminals of the input capacitor. n connect the top driver bootstrap capacitor, c1, closely to the bst1 and sw1 pins. connect the top driver bootstrap capacitor, c2, closely to the bst2 and sw2 pins. n connect the input capacitors, c in , and output capacitors, c out , closely to the power mosfets. these capaci- tors carry the mosfet ac current in boost and buck operation. n route snsn and snsp leads together with minimum pc trace spacing. avoid sense lines pass through noisy areas, such as switch nodes. ensure accurate current sensing with kelvin connections at the sense resistor. n connect the v c pin compensation network close to the ic, between v c and the signal ground pins. the capaci- tor helps to filter the effects of pcb noise and output voltage ripple voltage from the compensation loop. n connect the intv cc bypass capacitor, c vcc , close to the ic, between the intv cc and the power ground pins. this capacitor carries the mosfet drivers current peaks. an additional 0.1 f ceramic capacitor placed immediately next to the intv cc and pgnd pins can help improve noise performance substantially.
lt3791-1 22 37911f 98% efficient 60w (12v 5a) voltage regulator runs down to 3v v in typical a pplica t ions efficiency vs load current maximum output current vs v in 37911 ta02b load current (a) 0 1 efficiency (%) 90 95 100 80 70 50 85 75 55 60 65 2 3 4 5 v in = 3v v in = 6v v in = 12v v in = 28v v in = 48v input voltage (v) 3 0 maximum output current (a) 1 2 3 4 6 5 7 9 20 37911 ta02c 40 4 6 8 10 30 50 60 5 d4 c out2 100f 35v + v in 3v to 55v starts up from 5.5v intv cc tg1 bg1 snsp snsn bst1 bst2 bg2 pgnd sw2 tg2 rt lt3791-1 swi c3 1f c7 470nf ivinn v in ivinp ivinmon ismon clkout pwmout test1 en/uvlo ovlo v ref pwm ctrl r8 84.5k 300khz v c syncss sgnd r1 866k r2 576k r fault 100k r3 1m r4 57.6k r7 50 r in 0.003 c8 0.1f c ss 33nf c c 22nf 37911 ta02a r sense 0.004 isp isn fb c1 0.1f l1, 6.8h c2 0.1f d2d1 m2 m1 m3 m4 c vcc 4.7f c out 10f 25v 3 c in 4.7f 100v 4 r out 0.015 v out 12v 5a v o r5 73.2k r6 8.06k r c 5.1k d1, d2: nxp bat46wj d3: irf 10bq060 d4: irf 10bq040 d5, d6: diodes inc. bat46w l1: wurth elektronik we-hci 7443556680 m1, m2: renasas rjk0651dpb 60v ds m3, m4: vishay sir424dp 40v ds c out2 : suncon 35hvt100m d6 v o d5 d3 short c/10 ccm intv cc r9 100k r10 200k
lt3791-1 23 37911f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. 4.75 (.187) ref fe38 (aa) tssop rev c 0910 0.09 ? 0.20 (.0035 ? .0079) 0 ? 8 0.25 ref 0.50 ? 0.75 (.020 ? .030) 4.30 ? 4.50* (.169 ? .177) 1 19 20 ref 9.60 ? 9.80* (.378 ? .386) 38 1.20 (.047) max 0.05 ? 0.15 (.002 ? .006) 0.50 (.0196) bsc 0.17 ? 0.27 (.0067 ? .0106) typ recommended solder pad layout 0.315 0.05 0.50 bsc 4.50 ref 6.60 0.10 1.05 0.10 4.75 ref 2.74 ref 2.74 (.108) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc fe package 38-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1772 rev c) exposed pad variation aa p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings.
lt3791-1 24 37911f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2012 lt 0812 ? printed in usa r ela t e d p ar t s typical a pplica t ion part number description comments lt3791 60v, 4-switch, synchronous buck-boost led driver controller v in : 4.7v to 60v, v out range: 1.2v to 60v, true color pwm ?, analog, i sd < 1a, tssop-38e packages lt c ? 3780 high efficiency, synchronous, 4-switch buck-boost controller v in : 4v to 36v, v out range: 0.8v to 30v, i sd < 55a, ssop-24, qfn-32 packages ltc3789 high efficiency, synchronous, 4-switch buck-boost controller v in : 4v to 38v, v out range: 0.8v to 38v, i sd < 40a, 4mm w 5mm qfn-28, ssop-28 packages LT3755/LT3755-1 LT3755-2 high side 60v, 1mhz led controller with true color 3000:1 pwm dimming v in : 4.5v to 40v, v out range: 5v to 60v, 3000:1 true color pwm , analog, i sd < 1a, 3mm w 3mm qfn-16, msop-16e packages lt3756/lt3756-1 lt3756-2 high side 100v, 1mhz led controller with true color 3000:1 pwm dimming v in : 6v to 100v, v out range: 5v to 100v, 3000:1 true color pwm , analog, i sd < 1a, 3mm w 3mm qfn-16, msop-16e packages lt3596 60v, 300ma step-down led driver v in : 6v to 60v, v out range: 5v to 55v, 10000:1 true color pwm , analog, i sd < 1a, 5mm w 8mm qfn-52 package lt3743 synchronous step-down 20a led driver with thee-state led current control v in : 5.5v to 36v, v out range: 5.5v to 35v, 3000:1 true color pwm , analog, i sd < 1a, 4mm w 5mm qfn-28, tssop-28e packages 2.5a buck-boost 36v sla battery charger 50 470nf pv in 9v to 58v intv cc tg1 bg1 snsp snsn bst1 bst2 bg2 pgnd sw2 tg2 rt lt3791-1 swi r in 0.003 short ivinn i vinp 1f v in ivinmon pwmout ismon clkout en/uvlo ovlo intv cc 200k v ref pwm ctrl charge current control sgnd 84.5k 300khz d1, d2: bat46wj l1: coilcraft ser2915l-103k m1-m4: renesas rjk0651dpb m5: nxp nx7002ak c in2 : nippon chemi-con emza630ada101mja0g c out2 : suncon 35hvt220m v c sync ss c/10 ccm 20k 50 intv cc 57.6k 30.9k 499k 0.1f 22nf 22nf 1f 37911 ta03 c in2 100f 63v r sense 0.004 isp isn fb r bat 0.04 2.5a charge 36v sla battery agm type 41v float 44v charge at 25c 0.1f 0.1f l1 10h 4.7f m2 m1 m3 m4 d2 d1 c out2 220f 35v c out 4.7f 50v 2 1.00m 30.1k 402k m5 2.2k c in 4.7f 100v 2 + + + test1 100k

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